1. Field of the Invention
The present invention relates generally to circuitry, and more specifically to circuitry that includes a phase locked loop (PLL).
2. Background
Phase locked loops (PLLs) are used in any of a variety of systems, such as wireless and wire line communication systems, to synchronize signals.
In a PLL, a phase detector compares a feedback signal and a reference signal to generate a phase error signal. The phase error signal indicates a phase difference between the feedback signal and the reference signal. A charge pump provides a charge based on the phase error signal. A loop filter provides a voltage based on the charge. A voltage controlled oscillator (VCO) generates a system output signal having a frequency that is based on the voltage provided by the loop filter. A divider divides the frequency of the system output signal by a value to generate the feedback signal. The value utilized by the divider can be an integer or a non-integer.
Utilizing an integer value to generate the feedback signal provides a system output signal having a frequency that is an integer multiple of the frequency of the reference signal. Utilizing a non-integer value enables the PLL to provide a system output signal having a frequency that is a non-integer multiple of the frequency of the reference signal. However, generating the non-integer value gives rise to spurs. For example, the system output signal can have sidebands that negatively impact the performance of the PLL. Such spurs can reduce the signal-to-noise ratio (SNR) of the reference signal and/or degrade the bit error rate (BER) of the PLL.
What is needed, then, is a system and method that addresses one or more of the aforementioned shortcomings of conventional PLLs and feedback techniques.
In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.